1. Field of the Invention
The present invention relates to a vertical type semiconductor device and a method for producing the same.
2. Description of Related Arts
Various technologies have so far been developed for lowering the ON resistance R.sub.on, the resistance in the operating state, of a power MOS, especially of a vertical type DMOS (Double Diffused MOS) transistor. The ON resistance R.sub.on of a vertical type MOS transistor, as shown in FIG. 16, consists of the following components: EQU R.sub.on =R.sub.cont +R.sub.s +R.sub.ch +R.sub.D +R.sub.JFET +R.sub.epi +R.sub.sub +R.sub.B, (1)
where R.sub.cont represents the contact resistance, R.sub.s the source resistance, R.sub.ch the channel resistance, R.sub.D the depletion resistance, R.sub.JFET the JFET resistance, R.sub.epi the epitaxial layer resistance, R.sub.sub the substrate resistance, and R.sub.B the back side contact resistance.
The channel resistance R.sub.ch is given by the following expression (refer to "IEEE Transactions on Electron Devices", Vol. ED-27, No. 2, pp. 356-367, published in February, 1980). ##EQU1## where W represents the channel width, L.sub.eff the effective channel length given by K(X.sub.chpj-X.sub.N+j) (where X.sub.chpj represents the diffusion depth of the P.sup.- channel region 41, X.sub.N+j the diffusion depth of the N.sup.+ source region 42, and K a constant below unity, refer to FIG. 17), C.sub.o the gate capacity per unit area, .mu..sub.E the mobility, V.sub.TE the threshold voltage, and V.sub.G the gate voltage.
The depletion resistance R.sub.D is expressed as ##EQU2## where L.sub.eff ' represents the depletion mode effective channel length, .mu..sub.D the mobility of the accumulation layer, and V.sub.TD the depletion mode threshold voltage.
JFET resistance R.sub.JFET is expressed as ##EQU3## where L.sub.G represents the line width of the polysilicon gate electrode member 43 (refer to FIG. 17) and .rho. represents the specific resistance of epitaxial layer.
Epitaxial layer resistance R.sub.epi is expressed as ##EQU4## where .alpha., a, and h represent constants.
Reduction in the ON resistance R.sub.on is achieved, with respect to the channel resistance R.sub.ch for example, by decreasing the diffusion depth X.sub.chpj of the P.sup.- channel region 41 or by increasing the diffusion depth X.sub.N+j of the N.sup.+ source region 42 to thereby decrease L.sub.eff shown in FIG. 17, according to the expression (2). As to the JFET resistance R.sub.JFET the JFET resistance R.sub.JFET can be reduced by increasing the line width L.sub.G of the polysilicon gate electrode 43 or by increasing the concentration of epitaxial layer (that means lowering the specific resistance .rho.), according to the expression 4. Further, as to the epitaxial layer resistance R.sub.epi, the epitaxial layer resistance R.sub.epi can be reduced by increasing the concentration of epitaxial layer (that means lowering the specific resistance .rho.), according to the expression 5.